| Name | Size | I/O | Description |
|---|---|---|---|
| ctl_tx_test_pattern_* | 1 | I | Test pattern generation enable for the TX core.
A value of 1 enables test mode as defined in Clause 82.2.10.
Corresponds to MDIO register bit 3.42.3 as defined in Clause 82.3.
Generates a scrambled idle pattern. This port is available when the AXI4-Lite interface is not selected. |
| ctl_tx_enable_* | 1 | I | TX Enable. This signal is used to enable the
transmission of data when it is sampled as a 1. When sampled as a 0,
only idles are transmitted by the CORE. This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA. |
| ctl_tx_fcs_ins_enable_* | 1 | I | Enable FCS insertion by the TX core. If this
bit is set to 0, the 40G/50G High Speed Ethernet Subsystem does not add FCS to packet.
It his bit is set to 1, the 40G/50G High Speed Ethernet Subsystem
calculates and adds the FCS to the packet. This input cannot be
changed dynamically between packets. This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA. |
| ctl_tx_ipg_value_* | 4 | I | This signal might be optionally present. The
ctl_tx_ipg_value defines the target average minimum Inter Packet Gap
(IPG, in bytes) inserted between rx_serdes_clk packets. Valid values
are 8 to 12. The ctl_tx_ipg_value can also be programmed to a value
in the 0 to 7 range, but in that case, it is interpreted as meaning
"minimal IPG", so only Terminate code word IPG is inserted; no Idles
are ever added in that case and that produces an average IPG of
around 4 bytes when random-size packets are transmitted. This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA and Include FIFO Logic is disabled. |
| ctl_tx_send_lfi_* | 1 | I | Transmit Local Fault Indication (LFI) code
word. Takes precedence over RFI. This port is available when core type is Ethernet MAC+PCS/PMA. |
| ctl_tx_send_rfi_* | 1 | I | Transmit Remote Fault Indication (RFI) code
word. This port is available when core type is Ethernet MAC+PCS/PMA. |
| ctl_tx_send_idle_* | 1 | I | Transmit Idle code words. If this input is
sampled as a 1, the TX path only transmits Idle code words. This
input should be set to 1 when the partner device is sending Remote
Fault Indication (RFI) code words. This port is available when core type is Ethernet MAC+PCS/PMA. |
| ctl_tx_custom_preamble_enable_* | 1 | I | When asserted, this signal enables the use of
tx_preamblein as a custom preamble instead of inserting a standard
preamble. This port is available when the AXI4-Lite interface is not selected and core type is Ethernet MAC+PCS/PMA and Include FIFO Logic is disabled. |
| ctl_tx_ignore_fcs_* | 1 | I | Enable FCS error checking at the AXI4-Stream
interface by the TX core. This input only has effect when
ctl_tx_fcs_ins_enable is Low. If this input is Low and a packet with
bad FCS is being transmitted, it is not binned as good. If this
input is High, a packet with bad FCS is binned as good. The error is flagged on the signals stat_tx_bad_fcs and stomped_fcs, and the packet is transmitted as it was received. Statistics are reported as if there was no FCS error. This port is available when the AXI4-Lite interface is nnotot selected and core type is Ethernet MAC+PCS. |
| stat_tx_total_packets_* | 1 | O | Increment for the total number of packets
transmitted. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_total_bytes_* | 5 | O | Increment for the total number of bytes
transmitted. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_total_good_packets_* | 1 | O | Increment for the total number of good packets
transmitted. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_total_good_bytes_* | 14 | O | Increment for the total number of good bytes
transmitted. This value is only non-zero when a packet is
transmitted completely and contains no errors. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_64_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 64 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_65_127_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 65 to 127 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_128_255_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 128 to 255 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_256_511_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 256 to 511 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_512_1023_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 512 to 1,023 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_1024_1518_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 1,024 to 1,518 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_1519_1522_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 1,519 to 1,522 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_1523_1548_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 1,523 to 1,548 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_1549_2047_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 1,549 to 2,047 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_2048_4095_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 2,048 to 4,095 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_4096_8191_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 4,096 to 8,191 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_8192_9215_bytes_* | 1 | O | Increment for good and bad packets transmitted
that contain 8,192 to 9,215 bytes. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_small_* | 1 | O | Increment for all packets that are less than 64
bytes long. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_packet_large_* | 1 | O | Increment for all packets that are more than
9,215 bytes long. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_bad_fcs_* | 1 | O | Increment for packets greater than 64 bytes
that have FCS errors. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_frame_error_* | 1 | O | Increment for packets with tx_errin set to
indicate an EOP abort. This port is available when core type is Ethernet MAC+PCS/PMA. |
| stat_tx_local_fault_* | 1 | O | A value of 1 indicates the receive decoder state machine is in the TX_INIT state. This output is level sensitive. |
| stat_tx_fifo_error_* | 1 | O | Transmit clock compensation First In First Out
(FIFO) error indicator. A value of 1 indicates the clock
compensation FIFO under or overflowed. This condition only occurs if
the PPM difference between the transmitter clock and the local
reference clock is greater than ±200 ppm. If this output is sampled as a 1 in any clock cycle, the corresponding port must be reset to resume proper operation. This port is available when core type is Ethernet PCS/PMA. |