Ports under this section are available when Enable Additional GT Control/Status and DRP Ports is selected and GT in Core option is selected from the GT Selection and Configuration tab. Refer to the GT user guide for the port description.
Name | Size | I/O | Description |
---|---|---|---|
gt_dmonitorout_* | 34/68 | O | Port width: 34 bits for the 50G single core and 68 bits for 40G. |
gt_eyescandataerror_* | 2/4 | O | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_eyescanreset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_eyescantrigger_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_pcsrsvdin_* | 32/64 | I | Port width: 32 bits for the 50G single core and 64 bits for 40G. |
gt_rxbufreset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxbufstatus_* | 6/12 | O | Port width: 6-bit for the 50G single core and 12 bits for 40G. |
gt_rxcdrhold_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxcommadeten_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxdfeagchold_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxdfelpmreset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxlatclk_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxlpmen_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxpcsreset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxpmareset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxpolarity_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxprbscntreset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxprbserr_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxprbssel_* | 8/16 | I | Port width: 8-bit for the 50G single core and 16 bits for 40G. |
gt_rxrate_* | 6/12 | I | Port width: 6-bit for the 50G single core and 12 bits for 40G. |
gt_rxslide_in_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_rxstartofseq_* | 4/8 | O | Port width: 4-bit for the 50G single core and 8 bits for 40G. |
gt_txbufstatus_* | 4/8 | O | Port width: 4-bit for the 50G single core and 8 bits for 40G. |
gt_txdiffctrl_* | 10/20 | I | Port width: 10-bit for the 50G single core and 20 bits for 40G. |
gt_txinhibit_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_txlatclk_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_txmaincursor_* | 14/28 | I | Port width: 14-bit for the 50G single core and 28 bits for 40G. |
gt_txpcsreset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_txpmareset_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_txpolarity_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_txpostcursor_* | 10/20 | I | Port width: 10-bit for the 50G single core and 20 bits for 40G. |
gt_txprbsforceerr_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_txprbssel_* | 8/16 | I | Port width: 8-bit for the 50G single core and 16 bits for 40G. |
gt_txprecursor_* | 10/20 | I | Port width: 10-bit for the 50G single core and 20 bits for 40G. |
gtwiz_reset_tx_datapath_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gtwiz_reset_rx_datapath_* | 2/4 | I | Port width: 2 bits for the 50G single core and 4 bits for 40G. |
gt_common_drpclk | 1 | I | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_common_drpdo | 16 | O | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_common_drprdy | 1 | O | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_common_drpen | 1 | I | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_common_drpwe | 1 | I | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_common_drpaddr | 10 | I | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_common_drpdi | 16 | I | This port is available when the Include Shared Logic in core option is selected in the Shared Logic tab. |
gt_ch_drpclk_0 | 1 | I | |
gt_ch_drpdo_0 | 16 | O | |
gt_ch_drprdy_0 | 1 | O | |
gt_ch_drpen_0 | 1 | I | |
gt_ch_drpwe_0 | 1 | I | |
gt_ch_drpaddr_0 | 10 | I | |
gt_ch_drpdi_0 | 16 | I | |
gt_ch_drpclk_1 | 1 | I | |
gt_ch_drpdo_1 | 16 | O | |
gt_ch_drprdy_1 | 1 | O | |
gt_ch_drpen_1 | 1 | I | |
gt_ch_drpwe_1 | 1 | I | |
gt_ch_drpaddr_1 | 10 | I | |
gt_ch_drpdi_1 | 16 | I | |
gt_ch_drpclk_2 | 1 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpdo_2 | 16 | O | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drprdy_2 | 1 | O | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpen_2 | 1 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpwe_2 | 1 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpaddr_2 | 10 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpdi_2 | 16 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpclk_3 | 1 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpdo_3 | 16 | O | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drprdy_3 | 1 | O | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpen_3 | 1 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpwe_3 | 1 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpaddr_3 | 10 | I | This port is available when core speed is 40G / speed 50G with two cores. |
gt_ch_drpdi_3 | 16 | I | This port is available when core speed is 40G / speed 50G with two cores. |