The following figures show timing diagram waveforms for the AXI4-Lite interface.
Valid Write Transactions
Figure 1. AXI4-Lite User Side Write Transaction
Invalid Write Transactions
Figure 2. AXI4-Lite User Side Write Transaction with Invalid Write
Address
Valid Read Transactions
Figure 3. AXI4-Lite User Side Read Transaction
Invalid Read Transactions
Figure 4. AXI4-Lite User Side Read Transaction with Invalid Read
Address
