Xilinx IP - GT Quad Integration for Versal ACAP - 3.2 English

Xilinx® GT based IPs like Aurora, PCIe® , L Ethernet, and MRMAC provides Block Automation in the IP integrator to enable you to connect multiple Xilinx parent IPs to GT Quad seamlessly. IP Block Automation instantiates GT Quads and creates essential datapath, USRCLK and GT REFCLK connections.

Perform the following steps to connect multiple L Ethernet IPs using Block Automation:

1. Add L Ethernet IP using Add IP option in the IPI canvas.
2. Configure L Ethernet IP for number of lanes, line rates and so on.
3. Click Run_Block_Automation. In the Block Automation GUI, select one of the options Auto, Start_with_New_Quad, or Customized_Connections.
4. Perform steps 2 and 3 to add more L Ethernet IP instances based on your system need.

GT Quad parameters are propagated from its connected IPs when the design is validated. Hence all GT Quad parameters are marked Auto in the Transceiver Wizard GUI. However, you can change the Auto option to Manual for Transceiver Configs as shown in the following figure to fine tune parameters like insertion loss, drive strength, equalization, and other advanced settings. After toggling to Manual mode, any changes to the parent IP configurations followed by validation no longer propagate GT Quad parameters from parent IP to GT Quad. Manual changes should only be performed after all essential parent IP parameters are propagated to GT Quad.