Data Controller Clock - 3.2 English

Zynq DPU Product Guide (PG338)

Document ID
PG338
Release Date
2020-07-07
Version
3.2 English

The primary function of the data controller module is to schedule the data flow in the DPU IP. The data controller module works with m_axi_dpu_aclk. The data transfer between the DPU and external memory happens in the data controller clock domain, so m_axi_dpu_aclk is also the AXI clock for the AXI_MM master interface in the DPU IP. m_axi_dpu_aclk should be connected to the AXI_MM master clock.