IP Facts - 3.2 English

Zynq DPU Product Guide (PG338)

Document ID
PG338
Release Date
2020-07-07
Version
3.2 English
DPU IP Facts Table
Core Specifics
Supported Device Family Zynq®-7000 SoC and Zynq® UltraScale+™ MPSoC Family
Supported User Interfaces Memory-mapped AXI interfaces
Resources See DPU Configuration.
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Constraints File Xilinx Design Constraints (XDC)
Supported S/W Driver Included in PetaLinux
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation N/A
Synthesis Vivado® Synthesis
Support
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. Linux OS and driver support information are available from DPU TRD or Vitis™ AI development kit.
  2. If the target device is Zynq-7000 SoC, see the notifications in Development Flow.
  3. For the supported tool versions, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  4. The DPU is driven by instructions generated by the Vitis AI compiler. When the target neural network (NN), DPU hardware architecture, or AXI data width is changed, the related .elf file which contains DPU instructions must be regenerated.