“GT Selection and Configuration”选项卡支持您配置核的串行收发器功能。
图 1. 适用于 UltraScale/UltraScale+ 的“GT Selection and Configuration”选项卡
图 2. 适用于 Versal ACAP 的“GT Selection and Configuration”选项卡
选项 | 值 | 默认值 |
---|---|---|
GT Location | ||
选择将 GT IP 包含在核中还是包含在设计示例中 | Include GT subcore in core Include GT subcore in example design |
Include GT subcore in core |
GT Clock 3 | ||
GT RefClk (MHz) 1 | 161.1328125 | 161.1328125 |
195.3125 | ||
201.4160156 | ||
257.8125 | ||
322.265625、312.5、156.25 和 322.265625 | ||
GT DRP Clock (MHz) | 10.00 - 250.00 MHz | 100.00 |
Core to Transceiver Association | ||
GT 类型 | GTH、GTY 和 GTM | GTY |
GT 选择 (PLL Selection) | 选项基于器件/封装四通道组。例如: Quad X0Y1 Quad X0Y2 Quad X0Y3 GTM_DUAL_X0Y0 如果 GT 类型选为 GTM,则 GTM 双通道列表可供选择。例如:GTM_DUAL_X0Y0 GTM_DUAL_X0Y1 |
Quad X0Y0 |
Lane-00 到 Lane-03 | 根据器件/封装自动填充。 例如,如果 Speed = 50G 且 Num of Cores = 2(或者 Speed = 40G 且 Num of Cores = 1)并且 GT Selection = Quad X0Y1,则 4 个 GT 通道为: X0Y4 X0Y5 X0Y6 X0Y7 |
|
RX Equalization Mode | Auto LPM DFE | Auto |
RX Insertion Loss at Nyquist (dB) | 取决于 GT Wizard | 30 |
其它 | ||
Enable Pipeline Register | 0、1 | 0 |
Enable Additional GT Control and Status Ports | 0、1 | 0 |
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