40G/50G High Speed Ethernet 子系统 PCS 使用独立的 RX 和 TX 时钟域，其中 RX 和 TX 由 3 个时钟域组成，如下图所示。 图 1. PCS 时钟 Page-1 Sheet.1 RX part of SerDes RX part of SerDes Sheet.2 RX lane buffer RX lane buffer Sheet.3 RX PCS 64B66B decode de-scrambling RX PCS 64B66B decode de-scrambling Sheet.4 RX management logic RX management logic Sheet.5 Sheet.6 Sheet.7 MAC MAC Sheet.8 Sheet.9 Sheet.10 Example Design [Sim/Synth/PnR] core clocks and resets Sheet.11 Example Design [Sim/Synth/PnR] 25 Gb/s Phy x2 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Example Design [Sim/Synth/PnR] status and control Sheet.16 Example Design [Sim/Synth/PnR] 50GMII interface Sheet.17 TX part of SerDes TX part of SerDes Sheet.18 TX lane buffer TX lane buffer Sheet.19 TX PCS 64B66B encode de-scrambling TX PCS 64B66B encode de-scrambling Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 TX management logic TX management logic Sheet.25 Sheet.26 Example Design [Sim/Synth/PnR] status and control Sheet.27 Example Design [Sim/Synth/PnR] 50 Gb/s PCS Sheet.28 Sheet.29 Example Design [Sim/Synth/PnR] rx_serdes_clk Sheet.30 Example Design [Sim/Synth/PnR] rx_serdes_clk Sheet.31 Example Design [Sim/Synth/PnR] tx_serdes_refclk Sheet.32 Example Design [Sim/Synth/PnR] tx_serdes_refclk Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Example Design [Sim/Synth/PnR] tx_serdes_refclk Sheet.40 Sheet.41 Sheet.42 Example Design [Sim/Synth/PnR] rx_mii_clk Sheet.43 Sheet.44 Sheet.45 Sheet.46 X16601-030817 Sheet.47 Sheet.48 Sheet.49 X16601-080621 Dynamic connector