模块框图 - 3.2 简体中文

40G/50G High Speed Ethernet 子系统 v3.2 产品指南 (PG211)

Document ID
PG211
Release Date
2021-02-04
Version
3.2 简体中文

下图是 40/50 Gb/s 仅限 PCS 变体的模块框图。

图 1. PCS 变体 Page-1 Sheet.1 RX part of SerDes RX part of SerDes Sheet.2 RX lane buffer RX lane buffer Sheet.3 RX PCS 64B66B decode de-scrambling RX PCS 64B66B decode de-scrambling Sheet.4 RX management logic RX management logic Sheet.5 Sheet.6 Sheet.7 Sheet.8 MAC MAC Sheet.9 Example Design [Sim/Synth/PnR] 64+2 Sheet.10 Sheet.11 Sheet.12 Example Design [Sim/Synth/PnR] clocks and resets Sheet.13 Example Design [Sim/Synth/PnR] 25.78125 Gb/s PHY x 2 or 10.3125 Gb/s PHY x 4 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Example Design [Sim/Synth/PnR] rx_mii_drx_mii_c Sheet.18 Sheet.19 Example Design [Sim/Synth/PnR] control and status Sheet.20 Example Design [Sim/Synth/PnR] XLGMII/50GMII interface Sheet.21 TX part of SerDes TX part of SerDes Sheet.22 TX lane buffer TX lane buffer Sheet.23 TX PCS 64B66B encode de-scrambling TX PCS 64B66B encode de-scrambling Sheet.24 Sheet.25 Sheet.26 Example Design [Sim/Synth/PnR] 64+2 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Example Design [Sim/Synth/PnR] tx_mii_dtx_mii_c Sheet.32 TX management logic TX management logic Sheet.33 Sheet.34 Example Design [Sim/Synth/PnR] control and status Sheet.35 Example Design [Sim/Synth/PnR] 40/50 Gb/s PCS Sheet.36 Sheet.37 Sheet.38 X16600-030817 Sheet.39 Sheet.40 Sheet.41 X16600-080621