AXI4-Lite Interface - 3.3 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2020-12-16
Version
3.3 English
Table 1. AXI4-Lite Interface
Signal Direction Clock Domain Description
s_axi_aclk IN   AXI4-Lite I/F clock
s_axi_aresetn IN s_axi_aclk AXI4-LiteI/F reset
s_axi_awaddr[31:0] IN s_axi_aclk Write address
s_axi_awvalid IN s_axi_aclk Write address Valid
s_axi_awready OUT s_axi_aclk Write address Ready
s_axi_wdata[31:0] IN s_axi_aclk Write data
s_axi_wstrb[3:0] IN s_axi_aclk Write data byte valid. Tie to 4’hF
s_axi_wvalid IN s_axi_aclk Write valid
s_axi_wready OUT s_axi_aclk Write ready
s_axi_bresp OUT s_axi_aclk Write response
s_axi_bvalid OUT s_axi_aclk Write response valid
s_axi_bready IN s_axi_aclk Write response ready
s_axi_araddr[31:0] IN s_axi_aclk Read address
s_axi_arvalid IN s_axi_aclk Read address valid
s_axi_arready OUT s_axi_aclk Read address ready
s_axi_rdata[31:0] OUT s_axi_aclk Read data
s_axi_rresp OUT s_axi_aclk Read response
s_axi_rvalid OUT s_axi_aclk Read data valid
s_axi_rready IN s_axi_aclk Read ready