| Name | I/O | Description | Clock Domain |
|---|---|---|---|
| rx_clk_out | O |
rx_serdes_clk. Clocks RX interface between GT and the core. When in low latency buffer bypass mode this clock also clocks the AXI4-Stream RX interface. |
See Clocking. |
| tx_clk_out | O |
Clocks TX AXI4-Stream Interface and full TX datapath. |
See Clocking. |
| rx_reset | I | Reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The core handles synchronizing the rx_reset input to the appropriate clock domains within the core. | Async |
| tx_reset | I | Reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until clk is stable. The core handles synchronizing the tx_reset input to the appropriate clock domains within the core. | Async |
| rx_core_clk | I | The rx_core_clk signal is used to clock the receive AXI4-Stream interface. It is an input when the FIFO is included and is not an input port when in low latency mode with FIFO not included; instead it is driven internally by rx_clk_out. | rx_core_clk |