The clocking architecture for the Auto-Negotiation and Link Training blocks are illustrated in the following figure. Note that these blocks are not included unless the BASE-KR feature is selected. The Auto-Negotiation and Link Training blocks function independently from the MAC and PCS, and therefore they are on different clock domains.
Figure 1. Auto-Negotiation and Link Training Clocking
- rx_serdes_clk
- The rx_serdes_clk drives the RX line side logic for the Auto-Negotiation and Link Training.
- tx_serdes_clk
- The
tx_serdes_clkdrives the TX line side logic for the Auto-Negotiation and Link Training. The DME frame is generated on this clock domain. - AN_clk
- The AN_clk drives the Auto-Negotiation
state machine. All ability signals are on this clock domain. The
AN_clkcan be any convenient frequency. In the example design,AN_clkis connected to thedclkinput, which has a typical frequency of 75 MHz. TheAN_clkfrequency must be known to the Auto-Negotiation state machine because it is the reference for all timers.This clock is set by Vivado Integrated Design Environment (IDE) to the frequency as that of the Gt drp CLK setting entered in the GUI.