| Name | Size | I/O | Description |
|---|---|---|---|
| ctl_rx_enable_* | 1 | I | RX Enable. For normal operation, this input must be set to 1. When
this input is set to 0, after the RX completes the reception of the
current packet (if any), it stops receiving packets by keeping the
PCS from decoding incoming data. In this mode, there are no
statistics reported and the user interface is idle. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab and Select Core is Ethernet MAC+PCS/PMA-32/64-bit
or Ethernet
MAC.
|
| ctl_rx_check_preamble_* | 1 | I | When asserted, this input causes the Ethernet MAC to check the
preamble of the received frame. Note: This port is available when Include AXI4-Lite is not selected in the
Configuration tab and Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC.
|
| ctl_rx_check_sfd_* | 1 | I | When asserted, this input causes the Ethernet
MAC to check the start of frame Delimiter of the received
frame. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab and Select Core is Ethernet MAC+PCS/PMA-32/64-bit
or Ethernet
MAC.
|
| ctl_rx_force_resync_* | 1 | I | RX force resynchronization input. This signal is used to force the
RX path to reset, re-synchronize, and realign. A value of 1 forces
the reset operation. A value of 0 allows normal operation. Note: This input should normally be Low and should
only be pulsed (1 cycle minimum pulse) to force
realignment.
Note: This port
is available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit orEthernet MAC.
|
| ctl_rx_delete_fcs_* | 1 | I | Enable FCS removal by the RX core. If this bit is set to 0, the HSEC
core does not remove the FCS of the incoming packet. If this bit is
set to 1, the HSEC core deletes the FCS to the received packet. FCS
is not deleted for packets that are =<8 bytes long. This input
should only be changed while the corresponding reset input is
asserted. Note: This port is
available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC.
|
| ctl_rx_ignore_fcs_* | 1 | I | Enable FCS error checking at the user interface by the RX core. If
this bit is set to 0, a packet received with an FCS error is sent
with the rx_errout pin asserted during the last transfer (rx_eopout
and rx_enaout sampled 1). If this bit is set to 1, the HSEC core
does not flag an FCS error at the user interface. Note: The statistics are reported as if
the packet is good. The stat_rx_bad_fcs signal, however, reports
the error.
Note: This port
is available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC.
|
| ctl_rx_max_packet_len_* | 15 | I | Any packet longer than this value is considered to be oversized. If
a packet has a size greater than this value, the packet is truncated
to this value and the rx_errout signal is asserted along with the
rx_eopout signal. Packets less than 4 bytes are dropped. The allowed
value for this bus can range from 64 to 16,383. ctl_rx_max_packet_len[14] is reserved and must be set to 0. Note: This port is available
when Include AXI4-Lite
is not selected in the Configuration tab and Select Core is Ethernet MAC+PCS/PMA-32/64-bit
or Ethernet
MAC.
|
| ctl_rx_min_packet_len_* | 8 | I | Any packet shorter than this value is considered to be undersized.
If a packet has a size less than this value, the rx_errout signal is
asserted during the rx_eopout asserted cycle. Packets that are less
than 4 bytes are dropped. Note: This
port is available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC.
|
| ctl_rx_process_lfi_* | 1 | I | When this input is set to 1, the RX core expects and processes LF
control codes coming in from the transceiver. When set to 0, the RX
core ignores LF control codes coming in from the transceiver. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab and Select Core is Ethernet MAC+PCS/PMA-32/64-bit
or Ethernet
MAC.
|
| ctl_rx_test_pattern_* | 1 | I | Test pattern checking enable for the RX core. A value of 1 enables
test mode as defined in Clause 49. Corresponds to MDIO register bit
3.42.2 as defined in Clause 45. Checks for scrambled idle
pattern. Note: This port is
available when Include
AXI4-Lite is not selected in the Configuration
tab.
|
| ctl_rx_data_pattern_select_* | Corresponds to MDIO register bit 3.42.0 as defined in Clause
45. Note: This
port is available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit and the Include FIFO Logic is
disabled.
|
||
| ctl_rx_test_pattern_enable_* | Test pattern enable for the RX core. A value of 1 enables test
mode. Corresponds to MDIO register bit 3.42.2 as defined in Clause 45. Takes second precedence. Note: This
port is available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit and the Include FIFO Logic is
disabled.
|
||
| ctl_rx_prbs31_test_pattern_enable_* | 1 | I | Corresponds to MDIO register bit 3.42.1 as defined in Clause
45. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab and the Select Core is PCS/PMA 64-bit.
|
| ctl_rx_custom_preamble_enable_* | 1 | I | When asserted, this signal causes the preamble
to be presented on rx_preambleout. Note: This port is available when Include AXI4-Lite is not
selected in the Configuration tab and Select Core is Ethernet MAC+PCS/PMA-32/64-bit
and the Include FIFO
Logic is disabled or Select Core is Ethernet MAC.
|
| stat_rx_block_lock_* | 4 | O | Block lock status for each PCS lane. A value of 1 indicates that the corresponding lane has achieved block lock as defined in Clause 82. Corresponds to MDIO register bit 3.50.7:0 and 3.51.11:0 as defined in Clause 82.3. This output is level sensitive. |
| stat_rx_framing_err_valid_* | 1 | O | Valid indicator for stat_rx_framing_err. When 1 stat_rx_framing_err_0 is valid. |
| stat_rx_framing_err_* | 3 | O | RX sync header bits framing error. Each PCS Lane has a four-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding stat_rx_framing_err_valid is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters. |
| stat_rx_hi_ber_* | 1 | O |
High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by IEEE Std 802.3-2015. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3. This output is level sensitive. |
| stat_rx_bad_code_* | 2 | O | Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3-2015. This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3. |
| stat_rx_bad_code_valid_* | 1 | O | Indicates when stat_rx_bad_code is valid. Note: This port is available when
Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_error_valid_* | 1 | O | Indicates when stat_rx_error is valid. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_error_* | 8 | O | Test pattern mismatch increment. A non-zero
value in any cycle indicates a mismatch occurred for the test
pattern in the RX core. This output is only active when
ctl_rx_test_pattern is set. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_fifo_error_* | 1 | O | Indicates when RX FIFO goes into an underflow
or overflow condition. Note: This port
is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_total_packets_* | 2 | O | Increment for the total number of packets received. Note: This
port is available when Select
Core is Ethernet
PCS/PMA or Ethernet
MAC in the Configuration tab.
|
| stat_rx_total_good_packets_* | 1 | O | Increment for the total number of good packets received. This value
is only non-zero when a packet is received completely and contains
no errors. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_total_bytes_* | 6 | O | Increment for the total number of bytes received. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_total_good_bytes_* | 14 | O | Increment for the total number of good bytes received. This value is
only non-zero when a packet is received completely and contains no
errors. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_small_* | 2 | O | Increment for all packets that are less than 64 bytes long. Packets
that are less than 4 bytes are dropped. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_jabber_* | 1 | O | Increment for packets longer than ctl_rx_max_packet_len with bad
FCS. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MACin the
Configuration tab.
|
| stat_rx_packet_large_* | 1 | O | Increment for all packets that are more than 9,215 bytes long. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_oversize_* | 1 | O | Increment for packets longer than ctl_rx_max_packet_len with good
FCS. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_undersize_* | 2 | O | Increment for packets shorter than stat_rx_min_packet_len with good
FCS. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_toolong_* | 1 | O | Increment for packets longer than ctl_rx_max_packet_len with good
and bad FCS. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_fragment_* | 2 | O | Increment for packets shorter than stat_rx_min_packet_len with bad
FCS. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_64_bytes_* | 1 | O | Increment for good and bad packets received that contain 64
bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_65_127_bytes_* | 1 | O | Increment for good and bad packets received that contain 65 to 127
bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_128_255_bytes_* | 1 | O | Increment for good and bad packets received that contain 128 to 255
bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_256_511_bytes_* | 1 | O | Increment for good and bad packets received that contain 256 to 511
bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_512_1023_bytes_* | 1 | O | Increment for good and bad packets received that contain 512 to
1,023 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_1024_1518_bytes_* | 1 | O | Increment for good and bad packets received that contain 1,024 to
1,518 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_1519_1522_bytes_* | 1 | O | Increment for good and bad packets received that contain 1,519 to
1,522 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_1523_1548_bytes_* | 1 | O | Increment for good and bad packets received that contain 1,523 to
1,548 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_1549_2047_bytes_* | 1 | O | Increment for good and bad packets received that contain 1,549 to
2,047 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_2048_4095_bytes_* | 1 | O | Increment for good and bad packets received that contain 2,048 to
4,095 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_4096_8191_bytes_* | 1 | O | Increment for good and bad packets received that contain 4,096 to
8,191 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_8192_9215_bytes_* | 1 | O | Increment for good and bad packets received that contain 8,192 to
9,215 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_bad_fcs_* | 2 | O | Bad FCS indicator. The value on this bus indicates packets received
with a bad FCS, but not a stomped FCS. A stomped FCS is defined as
the bitwise inverse of the expected good FCS. This output is pulsed
for one clock cycle to indicate an error condition. Pulses can occur
in back-to-back cycles. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_packet_bad_fcs_* | 1 | O | Increment for packets between 64 and
ctl_rx_max_packet_len bytes that have FCS errors. Note: This port is available when
Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_stomped_fcs_* | 2 | O | Stomped FCS indicator. The value on this bus indicates packets were
received with a stomped FCS. A stomped FCS is defined as the bitwise
inverse of the expected good FCS. This output is pulsed for one
clock cycle to indicate the stomped condition. Pulses can occur in
back-to-back cycles. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_bad_preamble_* | 1 | O | Increment bad preamble. This signal indicates if the Ethernet packet
received was preceded by a valid preamble. A value of 1 indicates
that an invalid preamble was received. When an invalid preamble is detected, the stat_rx_bad_preamble signal is asserted regardless of the setting of the ctl_rx_check_preamble signal. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_bad_sfd_* | 1 | O | Increment bad SFD. This signal indicates if the Ethernet packet
received was preceded by a valid SFD. A value of 1 indicates that an
invalid SFD was received. When an invalid SFD is detected, the stat_rx_bad_sfd signal is asserted regardless of the setting of the ctl_rx_check_sfd signal. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_got_signal_os_* | 1 | O | Signal OS indication. If this bit is sampled as a 1, it indicates
that a Signal OS word was received. Signal OS should not be received in an Ethernet network. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_test_pattern_mismatch_* | 2 | O | Test pattern mismatch increment. A nonzero value in any cycle
indicates how many mismatches occurred for the test pattern in the
RX core. This output is only active when ctl_rx_test_pattern is set
to a 1. This output can be used to generate MDIO register 3.43.15:0
as defined in Clause 82.3. This output is pulsed for one clock
cycle. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_truncated_* | 1 | O | Packet truncation indicator. A value of 1 indicates that the current
packet in flight is truncated due to its length exceeding
ctl_rx_max_packet_len[14:0]. This output is pulsed for one clock
cycle to indicate the truncated condition. Pulses can occur in
back-to-back cycles. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_rx_local_fault_* | 1 | O | This output is High when stat_rx_internal_local_fault or stat_rx_received_local_fault is asserted. This output is level sensitive. |
| stat_rx_remote_fault_* | 1 | O | Remote fault indication status. If this bit is sampled as a 1, it
indicates a remote fault condition was detected. If this bit is
sampled as a 0, a remote fault condition does not exist. This output
is level sensitive. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_internal_local_fault_* | 1 | O | This signal goes High when an internal local fault is generated due
to any one of the following: test pattern generation, bad lane
alignment, or high bit error rate. This signal remains High as long
as the fault condition persists. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_received_local_fault_* | 1 | O | This signal goes High when enough local fault words are received
from the link partner to trigger a fault condition as specified by
the IEEE fault state machine. This signal remains High as long as
the fault condition persists. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit in the Configuration
tab.
|
| stat_rx_valid_ctrl_code_* | 1 | O | Indicates that a PCS block with a valid control code was received. |
| stat_rx_status | 1 | O | Indicates the link status. |