Shared logic includes all the shareable modules that can be present as part of the core or in the Example Design.
By default GT common, reset logic and clocking modules are present inside the IP core. In case of the following conditions, these modules will be placed outside the core so that they can be shared with other designs.
- When you select the Include GT subcore in example design option in the GT Selection and Configuration tab.
- When you select the Include Shared Logic in Example Design option in the Shared Logic tab.
When the shared logic in the example design is selected, a new xxv_ethernet_*_core_support.v module will be instantiated between the xxv_ethernet_*_exdes.v and DUT (that is, xxv_ethernet_*.v). This module will have all the sub modules that can be shared between multiple designs.
The following figure shows the implementation when shared logic is instantiated in the example design for single core.
The following figure shows the implementation when shared logic is instantiated in the example design for multiple cores.
The following modules are the part of shared logic wrapper.
- *_clocking_wrapper This module contains all the clk resources that can be shared with other designs.
- *_common_wrapper This module contains the GT common that can be shared with other designs.
- *_reset_wrapper This module contains all the reset logics for the specific selected Vivado IDE configuration.