The dpu_2x clock gating option can reduce the
power consumption of the DPU. When the option
is enabled, the number of generated clk_dsp should be equal to
the number of DPU
cores. Each clk_dsp should be
set as a buffer with CE in the clock wizard IP. As shown in the following figure, three
clk_dsp_ce appear when the output clock is configured with
the CE. To enable the dpu_2x clock gating function, each
clk_dsp_ce port should be connected to the corresponding
dpu_2x_clk_ce port in the DPU.
Figure 1. Configure Clock Wizard with Buffer CE
After configuring the clock wizard, the clock_dsp_ce should be connected to the corresponding port in the DPU. The connections are shown in the following
figure.
Figure 2. Clock CE and DPU
Connections
