Features - 3.3 English

Zynq DPU Product Guide (PG338)

Document ID
PG338
Release Date
2021-02-03
Version
3.3 English

The DPU has the following features:

  • One AXI slave interface for accessing configuration and status registers.
  • One AXI master interface for accessing instructions.
  • Supports configurable AXI master interface with 64 or 128 bits for accessing data depending on the target device.
  • Supports individual configuration of each channel.
  • Supports optional interrupt request generation.
  • Some highlights of DPU functionality include:
    • Configurable hardware architecture core includes: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096
    • Maximum of four homogeneous cores
    • Convolution and deconvolution
    • Depthwise convolution
    • Max pooling
    • Average pooling
    • ReLU, ReLU6, and Leaky ReLU
    • Concat
    • Elementwise-Sum and Elementwise-Multiply
    • Dilation
    • Reorg
    • Fully connected layer
    • Softmax
    • Batch Normalization
    • Split