The DPU generates an interrupt to
signal the completion of a task. A high state on reg_dpu0_start signals the start of a
DPU task for DPU core0. At the end of the task, the
DPU generates an interrupt and bit0
in reg_dpu_isr is set to 1. The position of the active bit in the reg_dpu_isr depends on
the number of DPU cores. For example,
when DPU core1 finishes a task while
DPU core0 is still working,
reg_dpu_isr would maintain 2’b10.
The width of the dpu_interrupt signal is
determined by the number of DPU cores.
When the parameter DPU_NUM is set to 2, then the DPU IP contains two DPU cores, and the width of the dpu_interrupt signal is two.
The lower bit represents the DPU core0
interrupt and the higher bit represents the DPU core1 interrupt.
The interrupt connection between the DPU and the PS is described in the device tree file, which indicates the interrupt number of the DPU connected to the PS. Any interrupt pin may be used if the device tree file and Vivado assignments match. The reference connection is shown here.
- If the softmax option is enabled, then the softmax interrupt should be correctly connected to the PS according to the device tree description.
- irq7~irq0 corresponds to pl_ps_irq0[7:0].
- irq15~irq8 corresponds to pl_ps_irq1[7:0].