The DPU top-level interfaces are shown in the following figure.
Figure 1.
Core Ports 
The DPU I/O signals are listed and described in the table below.
| Signal Name | Interface Type | Width | I/O | Description |
|---|---|---|---|---|
| S_AXI | Memory mapped AXI slave interface | 32 | I/O | 32-bit memory mapped AXI interface for registers. |
| s_axi_aclk | Clock | 1 | I | AXI clock input for S_AXI |
| s_axi_aresetn | Reset | 1 | I | Active-Low reset for S_AXI |
| dpu_2x_clk | Clock | 1 | I | Input clock used for DSP blocks in the DPU. The frequency is twice that of m_axi_dpu_aclk. |
| dpu_2x_resetn | Reset | 1 | I | Active-Low reset for DSP blocks |
| m_axi_dpu_aclk | Clock | 1 | I | Input clock used for DPU general logic. |
| m_axi_dpu_aresetn | Reset | 1 | I | Active-Low reset for DPU general logic |
| DPUx_M_AXI_INSTR | Memory mapped AXI master interface | 32 | I/O | 32-bit memory mapped AXI interface for DPU instructions. |
| DPUx_M_AXI_DATA0 | Memory mapped AXI master interface | 64 or 128 | I/O | 64-bit AXI interface for Zynq-7000 series and 128-bit for Zynq UltraScale+ MPSoC series. |
| DPUx_M_AXI_DATA1 | Memory mapped AXI master interface | 64 or 128 | I/O | 64-bit AXI interface for Zynq-7000 series and 128-bit for Zynq UltraScale+ MPSoC series. |
| dpu_interrupt | Interrupt | 1~4 | O | Active-High interrupt output from DPU. The data width is determined by the number of DPU cores. |
| SFM_M_AXI (optional) | Memory mapped AXI master interface | 128 | I/O | 128-bit memory mapped AXI interface for softmax data. |
| sfm_interrupt (optional) | Interrupt | 1 | O | Active-High interrupt output from softmax module. |
| dpu_2x_clk_ce (optional) | Clock enable | 1 | O | Clock enable signal for controlling the input DPU 2x clock when DPU 2x clock gating is enabled. |
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