Revision History - 3.3 English

Zynq DPU Product Guide (PG338)
Document ID
PG338
Release Date
2021-02-03
Version
3.3 English

The following table shows the revision history for this document.

Section Revision Summary
02/03/2021 Version 3.3
Clocking and Resets Updated Configuring Clock Wizard.
12/17/2020 Version 3.3
Entire document
  • Added Elementwise-Multiply function.
  • Added Max Reduce function.
  • Added constrain of Convolution and Deconvolution in Table 7.
  • Updated figures.
07/07/2020 Version 3.2
Entire document
  • Added Average Pool and BatchNormal in Table 7.
  • Added resources increment table of Average Pool, LeakyReLU, Depthwise conv, and Softmax .
  • Deleted the detailed description of Vivado flow and Vits flow in Chapter 7. For more details see the DPU_TRD github.
03/23/2020 Version 3.2
Entire document
  • Updated the Vivado flow and Vitis flow for Target Version of 1.4.1.
  • Replaced the description of DNNDK and DNNC to Vitis AI and Vitis AI Compiler.
  • Updated the maximum of DPU core number from three to four and modified the descriptions accordingly.
12/02/2019 Version 3.1
Entire document Updated the flow for Vitis™ device support.
08/13/2019 Version 3.0
Vitis AI Development Kit Updated description.
Configuration Options Added description in RAM Usage, Channel Augmentation, and updated numbers in Softmax section.
Advanced Tab Added note in DSP Cascade and updated LUT numbers for High DSP in Resources for Different DSP Usage table.
Build the PetaLinux Project Updated code.
07/31/2019 Version 3.0
Overview Updated whole chapter.
Product Specification Updated whole chapter.
Table 1: DPU Signal Description Added dpu_2x_clk_ce description.
DPU Configuration Updated whole chapter.
Introduction Updated description.
Table 7: Deep Neural Network Features and Parameters Supported by DPU Updated Depthwise Convolution and Max Pooling descriptions.
Configuration Options Updated figures. Added Channel Augmentation and dpu_2x Clock Gating sections and updated all description sections.
Clocking and Resets Updated whole chapter.
Add CE for dpu_2x_clk Added section.
Development Flow Updated whole chapter.
Add DPU IP into Repository or Upgrade DPU from a Previous Version Updated section.
Customizing and Generating the Core in Zynq-7000 Devices Updated figure.
Example Design Updated whole chapter.
DPU Configuration Updated section.
06/07/2019 Version 2.0
Vitis AI Development Kit Added description.
Table 1: DPU Signal Description Added softmax descriptions.
Interrupts Updated notes.
Table 7: Deep Neural Network Features and Parameters Supported by DPU Added Depthwise Convolution.
Configuration Options Added some new features: depthwise convolution, average pooling, ReLU type, softmax. Updated some figures of DPU GUI. Added description about s-axi clock mode.
Table 12: Performance of Different Models Updated table.
Table 13: I/O Bandwidth Requirements for DPU-B1152 and DPU-B4096 Updated table.
Register Clock Fixed the recommended frequency for DPU clock.
Configuring Clock Wizard Updated description and figure.
Add CE for dpu_2x_clk Updated description and figure.
Configure DPU Parameters Updated figure.
Connecting a DPU to the Processing System in the Zynq UltraScale+ MPSoC Updated section.
Assign Register Address for DPU Updated note.
Device Tree Added section.
Customizing and Generating the Core in Zynq-7000 Devices Added section.
Design Files Updated figure.
DPU Configuration Updated figure.
Software Design Updated section.
03/26/2019 Version 1.2
Build the PetaLinux Project Updated description.
Build the Demo Updated figure.
Demo Execution Updated code.
03/08/2019 Version 1.1
Table 6: reg_dpu_base_addr Updated description.
Figure 10: DPU Configuration Updated figure.
Build the PetaLinux Project Updated code.
Build the Demo Updated description.
03/05/2019 Version 1.1
Example Design Added chapter regarding the DPU targeted reference design.
02/28/2019 Version 1.0
Initial release. N/A