reg_dpu_reset - 3.3 English

Zynq DPU Product Guide (PG338)

Document ID
PG338
Release Date
2021-02-03
Version
3.3 English

The reg_dpu_reset register controls the resets of all DPU cores integrated in the DPU IP. The lower four bits of this register control the reset of up to four DPU cores. All the reset signals are active-High. The details of reg_dpu_reset are shown in the following table.

Table 1. reg_dpu_reset
Register Address Offset Width Type Description
reg_dpu_reset 0x004 32 R/W [n] – DPU core n reset