DDR Configuration - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

The page allows you to set the DDR controller configurations.

Figure 4-12: DDR Controller Options

X-Ref Target - Figure 4-12

Block_Design_2.png

Enable DDR Controller Enable DDR controller for Zynq® UltraScale+ MPSoC PS.