Because there are only up to 78 MIO available ports, many peripheral I/O ports beyond these can still be routed to the programmable logic through the Extended MIO (EMIO) interface. Alternative routing for IOP interfaces through programmable logic enables you to take full advantage of the IOP available in the processing system.
The EMIO for I2C, SPI flash memory, Ethernet management data input/output (MDIO), Arm® JTAG (PJTAG), SDIO, GPIO 3-state enable signals are inverted in the Processing System IP core.
The Zynq UltraScale+ MPSoC Processing System core allows you to select GPIO up to 96 bits. The Zynq UltraScale+ MPSoC Processing System has control logic to adjust user-selected width to flow into processing system.
See MIO Voltage Standard .