One external tamper interrupt is mapped to CSU through MIO. There are three interrupts from CSU (PS) to PL as CSU WDT Interrupt, CSU DMA Interrupt, and CSU interrupt.
The CSU Interrupt is used to indicate that something in the CSU logic has caused an interrupt. The CSU interrupt status register holds the interrupt bits for all of the CSU logic except for the DMA. The following values can cause an interrupt in the CSU:
For more information, see the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .
• AES done – Bit to notify Advanced Encryption done.
• PL INIT complete – Bit to indicate PL initialization is complete.
• AES error – Bit to indicate Advanced Encryption error.
• RSA done – Bit to Indicate RSA Encryption done.
• PL POR_B – Bit to indicate PL power on reset status.
• TMR fatal error – Bit to indicate Triple-Mode Redundant (TMR) fatal error
• SHA done – Bit to indicate Secure Hash Algorithm Encryption done.
• PL SEU error flag – Bit to indicate Single Even Upset error.
• APB SLVERR – An error bit to indicate the failure of a transfer.
• PL CFG done – Status bit to indicate PL configuration complete.
• PCAP FIFO overflow – Status bit to indicate Processor Configuration Access Port FIFO overflow.
• CSU RAM ECC error – Bit to indicate CSU RAM ECC error.
The CSU_DMA_IRQ will alert the system that the DMA has generated an interrupt. The CSU WDT Interrupt is from the CSU watch dog timer interrupt.