PL Clocks - 3.4 English

Zynq UltraScale+ MPSoC Processing System Product Guide (PG201)

Document ID
PG201
Release Date
2022-05-11
Version
3.4 English

The Processing System IP provides four clocks to the PL. Processing System IP enables configuration of these clocks to be used in the PL. Processing System IP inserts a BUFG for each of the PL clocks through parameters similar to C_FCLK_CLK0_BUF. Programmable Logic clocks are configured for 99.99 MHz by default.