Note: For register information, see the Zynq UltraScale+ MPSoC Register Reference User Guide (UG1087) [Ref 2] .
The Processing System IP core provides access from PL masters to PS internal peripherals, and memory through AXI FIFO interface (AFI) interfaces. The Vivado IP integrator address editor provides various address segments with a fixed address for each slave interface. The availability of the address segments is controlled through the following addressing parameters.
• Detailed IOP address space : Provides individual address spaces for PS internal peripherals.
• Allow access to PS/SLCR registers : Allows address mapping to PS and system level control registers (SLCR) register space.
• Detailed PS/SLCR address space : Provides individual address spaces for PS/SLCR registers.
The PS address space accessible from the PL consists of DDR, OCM, static memory controller (SMC) memories, SLCR registers, PS I/O peripheral registers, and PS system registers. For more information, see the “System Addresses” chapter of the Zynq UltraScale All Programmable MPSoC Technical Reference Manual (UG1085) [Ref 1] .