AveragePool - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Release Date
2022-01-20
Version
3.4 English

The AveragePool option determines whether the average pooling operation will be performed on the DPUCZDX8G or not. The supported sizes range from 2x2, 3x3, …, to 8x8, with only square sizes supported.

The extra resources with Average Pool is listed in the following table.

Table 1. Extra LUTs of DPUCZDX8G with Average Pool
DPUCZDX8G Architecture Extra LUTs
B512(4x8x8) 1507
B800(4x10x10) 2016
B1024(8x8x8) 1564
B1152(4x12x12) 2352
B1600(8x10x10) 1862
B2304(8x12x12) 2338
B3136(8x14x14) 2574
B4096(8x16x16) 3081