Instantiating the Xilinx clock wizard IP
can implement the above circuit. In this reference design, the frequency of
s_axi_aclk is set to 100 MHz and m_axi_dpu_aclk is set to 325 MHz. Therefore, the frequency of the dpu_2x_clk should be set to 650 MHz accordingly. The recommended
configuration of the Clocking Options tab is shown in the following figure. Note: The parameter of the Primitive must be set to Auto.
Figure 1. Recommended Clocking Options of Clock Wizard
In addition, Matched Routing must be selected for m_axi_dpu_aclk and dpu_2x_clk in the Output
Clocks tab of the Clock Wizard IP. Matched Routing significantly reduces the skew between
clocks generated through BUFGCE_DIV blocks. The related configuration is shown in the
following figure.
Figure 2. Matched Routing in Clock Wizard
Note: Set the frequencies of the clkout
from High to Low. Figure (a) shows the correct sequence. The settings in figure (a) achieved
the dedicated clock design in the Summary page while the figure (b) did not. For more
details, refer to the
Clocking Wizard LogiCORE IP Product Guide
(PG065).
Figure 2. Comparison of clkout Frequency Sequence
