The DPUCZDX8G has the following features:
- One AXI slave interface for accessing configuration and status registers.
- One AXI master interface for accessing instructions.
- Supports individual configuration of each channel.
Some highlights of DPUCZDX8G functionality include:
- Configurable hardware architecture core includes: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096
- Maximum of four homogeneous cores
- Convolution and Transposed Convolution
- Depthwise convolution and Depthwise transposed convolution
- Max pooling
- Average pooling
- ReLU, ReLU6, and Leaky ReLU
- Elementwise-Sum and Elementwise-Multiply
- Fully connected layer
- Concat, Batch Normalization : supported by tool-chain