Port Descriptions - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Release Date
2022-01-20
Version
3.4 English

The DPUCZDX8G top-level interfaces are shown in the following figure.

Figure 1. Two DPU Kernel Ports

The DPUCZDX8G I/O signals are listed and described in the table below.

Table 1. DPUCZDX8G Signal Description
Signal Name Interface Type Width I/O Description
S_AXI Memory mapped AXI slave interface 32 I/O 32-bit memory mapped AXI interface for registers.
s_axi_aclk Clock 1 I AXI clock input for S_AXI
s_axi_aresetn Reset 1 I Active-Low reset for S_AXI
dpu_2x_clk Clock 1 I Input clock used for DSP blocks in the DPUCZDX8G. The frequency is twice that of m_axi_dpu_aclk.
dpu_2x_resetn Reset 1 I Active-Low reset for DSP blocks
m_axi_dpu_aclk Clock 1 I Input clock used for DPUCZDX8G general logic.
m_axi_dpu_aresetn Reset 1 I Active-Low reset for DPUCZDX8G general logic
DPUx_M_AXI_INSTR Memory mapped AXI master interface 32 I/O 32-bit memory mapped AXI interface for DPUCZDX8G instructions.
DPUx_M_AXI_DATA0 Memory mapped AXI master interface 128 I/O 128-bit for Zynq UltraScale+ MPSoC series.
DPUx_M_AXI_DATA1 Memory mapped AXI master interface 128 I/O 128-bit for Zynq UltraScale+ MPSoC series.
dpux_interrupt Interrupt 1 O Active-High interrupt output from DPUCZDX8G.
SFM_M_AXI (optional) Memory mapped AXI master interface 128 I/O 128-bit memory mapped AXI interface for softmax data.
sfm_interrupt (optional) Interrupt 1 O Active-High interrupt output from softmax module.
dpu_2x_clk_ce (optional) Clock enable 1 O Clock enable signal for controlling the input DPUCZDX8G 2x clock when DPUCZDX8G 2x clock gating is enabled.
  1. The softmax interface only appears when the softmax option in the DPUCZDX8G is enabled.