s_axi_aclk is used for the register
configuration module. This module receives the DPUCZDX8G configuration though the S_AXI interface. The S_AXI clock
can be configured as common with the M-AXI clock or as an independent clock. The
DPUCZDX8G configuration registers are
updated at a very low frequency and most of those registers are set at the start of a
task. The M-AXI is used as a high-frequency clock, Xilinx recommends setting the S-AXI clock as an independent clock with a
frequency of 100 MHz.
In the Vitis flow, the platform may provide only two clocks for the DPUCZDX8G IP. In this case, the S_AXI clock must be configured as common with the M-AXI clock.