reg_dpu_instr_addr - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Release Date
2022-01-20
Version
3.4 English

The reg_dpu_instr_addr register is used to indicate the instruction address of a DPUCZDX8G core. Each DPUCZDX8G core has a reg_dpu_instr_addr register. Only the lower 28-bits are valid. In the DPUCZDX8G processor, the real instruction-fetch address is a 40-bit signal which consists of the lower 28 bits of reg_dpu_instr_addr followed by 12 zero bits. The available instruction address for DPU ranges from 0x1000 to 0xFFFF_FFFF_FFFF_F000. The details of reg_dpu_instr_addr are shown in the following table.

Table 1. reg_dpu_instr_addr
Register Address Offset Width Type Description
reg_dpu0_instr_addr 0x20C 32 R/W Start address in external memory for DPUCZDX8G core0 instructions. The lower 28-bit is valid.
reg_dpu1_instr_addr 0x30C 32 R/W Start address in external memory for DPUCZDX8G core1 instructions. The lower 28-bit is valid.
reg_dpu2_instr_addr 0x40C 32 R/W Start address in external memory for DPUCZDX8G core2 instructions. The lower 28-bit is valid.
reg_dpu3_instr_addr 0x50C 32 R/W Start address in external memory for DPUCZDX8G core3 instructions. The lower 28-bit is valid.