Creating the Isolation Test SW Applications in Vitis 2021.1

Memory and Peripheral Protection Unit for PL Isolation in Zynq UltraScale+ Devices (XAPP1353)

Document ID
XAPP1353
Release Date
2022-05-04
Revision
1.1 English

This section describes how to use Vitis to create software that runs on the isolated system, created in the previous section. The following sections demonstrate five software projects that are created to test the features previously discussed. These projects and their functions are listed in the following table.

Table 1. Isolation Test Application Projects
Project Description
r5_fsbl FSBL running on R5_0
pmu_fw_u0 PMU firmware: event handler (prints to uart0)
pmu_fw_u1 PMU firmware: event handler (prints to uart1)
rpu_fault_injection Fault Injection code running on R5_0
apu_fault_injection Fault Injection code running on APU_0
Note: The Build HW Design in Vivado section should have exported the XSA hardware file to:
<your_path>/XmpuPL_ZUplus_v1.0a/zcu102_2021.1/xmpu_example/pl_isolation_lab.vitis/Base_Zynq_MPSoC_wrapper_hw_platform/Base_Zynq_MPSoC_wrapper.xsa
  1. If the pl_isolation_lab project is open in Vivado 2021.1, run the following steps:
  2. Select Tools>Launch Vitis IDE
  3. Select the workspace in Eclipse Launcher
    1. Workspace: <your_path>\XmpuPL_ZUplus_v1.0a\zcu102_2021.1\xmpu_example\pl_isolation_lab.vitis
    2. Click Launch
      Figure 1. Vitis IDE Launcher