10 MAC-only Clocking - 4.0 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2021-10-27
Version
4.0 English

The clocking architecture for the 10G MAC-only configuration is shown in Clocking. There are three clock domains as illustrated by the dashed lines.

Figure 1. Clocking Architecture for the 10G MAC-only Configuration

rx_mii_clk
The rx_mii_clk can be driven internally or externally. It is required that the clock be chosen to meet the IEEE 802.3 requirements of 156.25 MHz ± 100 ppm for 10 Gb/s operation.
tx_mii_clk
The tx_mii_clk can be driven internally or externally. It is required that the clock be chosen to meet the IEEE 802.3 requirements of 156.25 MHz ± 100 ppm for 10 Gb/s operation.
clk
The clock clk drives all the internal RX and TX core logic including the AXI4-Stream interface and control and status signals. The clock clk should be run at a frequency greater than or equal to 156.25 MHz.