AXI4-Lite Interface Implementation - 4.0 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2021-10-27
Version
4.0 English

In order to instantiate the AXI4-Lite interface to access the control and status registers of the xxv_ethernet_0 core, enable the Include AXI4-Lite check box in the Configuration Tab of the Vivado IDE. This option enables the xxv_ethernet_0_axi_if_top module (which contains xxv_ethernet_0_pif_registers with the xxv_ethernet_0_slave_2_ipif module). You can access the AXI4-Lite interface logic registers (control, status and statistics) from the xxv_ethernet_0_pkt_gen_mon module.

This mode enables the following features:

  • You can configure all the control (CTL) ports of the core through the AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface.
  • You can access all the status and statistics registers from the core through the AXI4-Lite interface. This operation is performed by reading the address locations for the status and statistics registers through register map.