Clocks and Resets - 4.0 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2021-10-27
Version
4.0 English
Table 1. Clocks and Resets
Signal Direction Clock Domain Description
ts_clk I N/A Free running clock which clocks system timer’s counters
ts_rst I ts_clk System timer reset active-High
tod_intr O ts_clk Interrupt asserted on 1-PPS event