Common Clock/Reset Signals

Common Clock/Reset Signals - 4.0 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID

PG210

Release Date

2021-10-27

Version

4.0 English

Table 1. Common Clock/Reset Signals
Name	Size	I/O	Description
sys_reset	1	I	Reset for core. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the core type is not Ethernet MAC 64-bit. This port is available when the Include GT subcore option in the example design is selected in the GT Selection and Configuration tab. The core type is either Ethernet MAC+PCS/PMA 32-bit or PCS/PMA 32-bit and timestamp is enabled.
dclk	1	I	Stable input clk to GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the core type is not Ethernet MAC 64-bit. This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab. The core type is either Ethernet MAC+PCS/PMA 32-bit or PCS/PMA 32-bit and timestamp is enabled.
sys_reset_0	1	I	Reset for core. Note: This port is available when Soft RS-FEC TX and Hard RS-FEC RX options are enabled and Include GT subcore in core option is selected in the GT Selection and Configuration tab and the core type is not Ethernet MAC 64-bit. The port is available when Soft RS-FEC TX and Hard RS-FEC RX options are enabled and Include GT subcore in example design option is selected in the GT Selection and Configuration tab and the core type is either Ethernet MAC+PCS/PMA 32-bit or PCS/PMA 32-bit and timestamp is enabled.
dclk_0	1	I	Stable input clk to GT. Note: This port is available when Soft RS-FEC TX and Hard RS-FEC RX options are enabled and Include GT subcore in core option is selected in the GT Selection and Configuration tab and the core type is not Ethernet MAC 64-bit. The port is available when Soft RS-FEC TX and Hard RS-FEC RX options are enabled and Include GT subcore in example design option is selected in the GT Selection and Configuration tab and the core type is either Ethernet MAC+PCS/PMA 32-bit or PCS/PMA 32-bit and timestamp is enabled.
gt_refclk_p	1	I	Differential input clk to GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core option is selected in the Shared Logic tab.
gt_refclk_n	1	I	Differential input clk to GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core option is selected in the Shared Logic tab.
qpll0clk_in	2/4	I	QPLL0 clock input. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab. Port width: 2-bit for 50G single core and 4bit for 40G one core / 50G two core.
qpll0refclk_in	2/4	I	QPLL0 ref clock input. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab. Port width: 2-bit for 50G single core and 4bit for 40G one core / 50G two core.
qpll1clk_in	2/4	I	QPLL1 clock input. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab. Port width: 2-bit for 50G single core and 4bit for 40G one core / 50G two core.
qpll1refclk_in	2/4	I	QPLL1 ref clock input. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab. Port width: 2-bit for 50G single core and 4bit for 40G one core / 50G two core.
gtwiz_reset_qpll0lock_in	1	I	QPLL0 lock reset input to the GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtwiz_reset_qpll0reset_out	1	O	QPLL0 lock reset output from the GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtwiz_reset_qpll1lock_in	1	I	QPLL1 lock reset input to the GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtwiz_reset_qpll1reset_out	1	O	QPLL1 lock reset output from the GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
tx_clk_out_*	1	O	TX user clock output from GT. Note: This port is available when the Select Core is Ethernet MAC+PCS/PMA 32/64-bit and the Include GT subcore in core option is selected in the GT Selection and Configuration tab. This port is available when the Select Core is Ethernet MAC+PCS/PMA 32/64-bit and GT type is GTM and Include GT subcore in example design option is selected in the Selection and Configuration tab.
tx_mii_clk_*	1	O	TX mii clock output from GT. Note: This port is available when the Select Core is Ethernet PCS/PMA 32/64-bit and the Include GT subcore in core option is selected in the GT Selection and Configuration tab. This port is available when the Select Core is Ethernet PCS/PMA 32/64-bit and GT type is GTM and Include GT subcore in example design option is selected in the Selection and Configuration tab.
rx_clk_out_*	1	O	RX user clock output from GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab. This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and GT type is GTM.
rx_serdes_clk_*	1	I	RX serdes clock input to core. Note: This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and GT type is not GTM.
rx_serdes_reset_*	1	I	RX serdes reset input to core Note: This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab.
rxrecclkout_*	1	O	RX recovered clock output from GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab.
tx_core_clk_*	1	I	TX Core clock input from GT wrapper. Note: This port is available when the Include GT subcore in example design option is selected in the GT Selection and Configuration tab and GT type is not GTM.
rx_core_clk _*	1	I	RX Core clock input to the core.
tx_reset_*	1	I	TX reset input to the core.
user_tx_reset_*	1	O	TX reset output for the user logic. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core option is selected in the Shared Logic tab.
gt_reset_tx_done_out_*	1	O	TX reset done signal from the GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
rx_reset_*	1	I	RX reset input to the core.
user_rx_reset_*	1	O	RX reset output for the user logic. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in core option is selected in the Shared Logic tab.
gt_reset_rx_done_out_*	1	O	RX reset done signal from the GT. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtwiz_reset_all_in*	1	I	gt_reset_all signal from the user. Note: Versal devices only. This port is available when the Control and Statistics interface is selected from the Configuration tab.
ctl_gt_reset_all_*	1	O	gt_reset_all signal from the AXI4-Lite register map. Note: This port is available when the Include AXI4-Lite is selected from the Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtwiz_tx_datapath_reset_in_*	1	I	gt_tx_reset signal from the user. Note: Versal devices only. This port is available when the Control and Statistics interface option is selected from the Configuration tab.
ctl_gt_tx_reset_*	1	O	gt_tx_reset signal from the AXI4-Lite register map. Note: This port is available when the Include AXI4-Lite option is selected from the Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtwiz_rx_datapath_reset_in_*	1	I	gt_rx_reset signal from the user. Note: Versal devices only. This port is available when the Control and Statistics interface is selected from the Configuration tab.
ctl_gt_rx_reset_*	1	O	gt_rx_reset signal from the AXI4-Lite register map. Note: This port is available when the Include AXI4-Lite is selected from the Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gt_reset_all_in_*	1	I	gt_reset_all signal from the reset_wrapper of shared logic wrapper. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gt_tx_reset_in_*	1	I	gt_tx_reset_in signal from reset_wrapper of shared logic wrapper. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gt_rx_reset_in_*	1	I	gt_rx_reset_in signal from reset_wrapper of shared logic wrapper. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gt_refclk_out	1	O	Indicates the GT_refclk output. Note: This port is available when the Include GT subcore in core option is selected in the GT Selection and Configuration tab and the Include Shared Logic in example design option is selected in the Shared Logic tab.
gtpowergood_out_*	1	O	Refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) or the UltraScale Architecture GTY Transceivers User Guide (UG578) for the port description.
TXOUTCLKSEL_IN_*	3	I	This port is used to select the clock source for the gtwizard TX output clock This port to be driven with 3'b101 as per preset.
RXOUTCLKSEL_IN_*	3	I	This port is used to select the clock source for the gtwizard RX output clock This port to be driven with 3'b101 as per preset.
gtm_txusrclk2_*	1	I	TX clock input to the core. Note: This port is available when Include GT subcore in example design option is selected from GT Selection and Configuration tab and GT type is GTM.
gtm_rxusrclk2_*	1	I	RX clock input to the core. Note: This port is available when Include GT subcore in example design option is selected from GT Selection and Configuration tab and GT type is GTM.