Example Design Hierarchy (GT in Example Design) - 4.0 English

When the 10/25G Ethernet subsystem is added to Vivado IP integrator, the Run Block Automation IP/Core and GT (Serial transceivers) will get connected with some helper blocks as per the core configuration. There is a reset interface IP, internal to 10/25G Ethernet IP, used to release TX/RX mstreset to the Versal device GT and check for TX/RX mstresetdone status and reset sequencing to GT.

Figure 1. Single Core with GT in Example Design Hierarchy

Figure 2. Single Core with GT in Example Design Hierarchy (Versal ACAP)

The previous figures show the instantiation of various modules and their hierarchy for a single core configuration of the xxv_ethernet_0 design when the GT (serial transceiver) is outside the IP Core, that is, in the example design. This hierarchical example design is delivered when you select the Include GT subcore in example design option from the GT Selection and Configuration tab.

The xxv_ethernet_0_core_support.v is present in the hierarchy when you select the Include GT subcore in example design option from the GT Selection and Configuration tab.

The user interface available for MAC/PCS configuration and PCS configuration configurations is the same as mentioned in the Overview topic.

The xxv_ethernet_0.v module instantiates the necessary the sync registers/retiming pipeline registers for the synchronization of data between the core and the GT.

The xxv_ethernet_0_pkt_gen_mon module is used to generate the data packets for sanity testing. The packet generation and checking is controlled by a Finite State Machine (FSM) module. Description of optional modules are as follows:

xxv_ethernet _0_sharedlogic_wrapper

This module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or Include Shared Logic in the Example Design from the Shared Logic tab. This module brings all modules that can be shared between multiple IP cores and designs outside the IP core.

xxv_ethernet _0_gt_wrapper

This module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab. This module is having instantiations of the GT along with various helper blocks. The clocking helper blocks are used to generate the required clock frequency for the core.

The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the xxv_ethernet_0 example design when the GT is in the example design.

Figure 3. Multiple Core with GT in Example Design Hierarchy

For Versal™ platforms, the gt_quad_base (GT Wizard for Versal device) will be a part of the example design only, and 10/25G Ethernet Subsystem IP and GT (Serial transceiver) IP will be connected in the block design using the IP integrator.

The following figure is a block design, where 10/25G Ethernet example design connected in the IP integrator. See the Vivado Design Suite Tutorial: Designing IP Subsystems Using IP Integrator (UG995) for more information on the IP integrator.

Note: When the 10/25G Ethernet subsystem is added to the Vivado IP integrator, the run Block Automation IP/Core and GT (Serial transceivers) will get connected with some helper blocks as per the core configuration. There is a reset interface IP, internal to 10/25G Ethernet IP, used to release TX/RX mstreset to Versal device GT and check for TX/RX mstresetdone status and reset sequencing to GT.

Figure 4. 10/25G Ethernet Block Design