Miscellaneous Status/Control Ports - 4.0 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2021-10-27
Version
4.0 English

The following table shows the miscellaneous status/control ports.

Table 1. Miscellaneous Status/Control Ports
Name I/O Clock Domain Description
dclk I Refer to Clocking. Dynamic Reconfiguration Port (DRP) clock input. The required frequency is set by providing the value in the GT DRP Clock field in the Vivado® IDE GT Selection and Configuration tab. This must be a free running input clock.
ctl_local_loopback I Async When High, this signal places the transceiver into the PMA loopback state.