The following figure shows the instantiation of various modules and their hierarchy for a single core configuration of xxv_ethernet_0 example design when the GT (serial transceiver) is inside the IP core. (Serial Transceiver will always be a part of the example design for Versal® ACAP).
Sync registers and pipeline registers are used for to synchronize the data between the core and the GT.
Clocking helper blocks are used to generate the required clock frequency for the core.
The following user interfaces are available for different configurations.
- MAC/PCS configuration:
- AXI4-Stream for datapath interface
- AXI4-Lite for control and statistics interface
- PCS configuration:
- MII for datapath interface
- AXI4-Lite for control and statistics interface
The xxv_ethernet_0_pkt_gen_mon
module is used to generate the data
packets for sanity testing. The packet generation and checking is controlled by a FSM
module.
The optional modules are described as follows:
- xxv_ethernet _0_trans_debug
- This module is present in the example design when you enable the Additional GT Control and Status Ports check box from the GT Selection and Configuration Tab in the Vivado IDE or Include GT subcore in example design option in the GT Selection and Configuration tab or the Runtime Switchable mode option in the in the Configuration tab. This module brings out all the GT channel DRP ports, and some control and status ports of the transceiver module out of the xxv_ethernet core.
- Retiming registers
- When you select the Enable Retiming
Register option from the GT Selection and Configuration Tab, it includes a single stage pipeline register
between core and the GT to ease timing, using the
gt_txusrclk2andgt_rxusrclk2for TX and RX paths respectively. However, by default two-stage registering is done for the signals between GT and the core. - TX / RX Sync register
- The TX Sync register double synchronizes the data from the core
to the GT with respect to the
tx_clk. The RX Sync register double synchronizes the data from the GT to the core with respect to therx_serdes_clk.Note: For Runtime Switchable, if Auto-Negotiation/Link training is selected in Vivado IDE, then AN operation will be performed only with the 25G data rate during switchings and LT will be performed in the mission mode.Note: If Auto-Negotiation/Link training is selected in Vivado IDE and the number of cores >= 3, then a Pblock constraint must be applied for the anlt_wrappers. The Pblock should be placed near to the selected transceivers (GT) and the size should be sufficient to fit the anlt_wrapper utilization. Refer to example_top.xdc for more information. Following is an example for a xcvu095-ffva2104-2-e device when four cores are selected and the transceivers are x0y4 to x0y7.Example:
create_pblock pblock_ANLT add_cells_to_pblock [get_pblocks pblock_ANLT] [get_cells -quiet [list DUT/inst/ i_*_top_0/i_*_*_ANLT_WRAPPER DUT/inst/i_*_top_1/i_*_ANLT_WRAPPER DUT/inst/ i_*_*_top_2/i_*_ANLT_WRAPPER DUT/inst/i_*_top_3/i_*_ANLT_WRAPPER]]resize_pblock [get_pblocks pblock_ANLT] -add {SLICE_X0Y5:SLICE_X40Y180}
The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the xxv_ethernet_0 example design.
