Ports - 4.0 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2021-10-27
Version
4.0 English

Ports Added

  • stat_rx_status
  • axi_ctl_core_mode_switch_*
  • rx_mii_clk
  • tx_mii_clk
  • clk

Ports Deleted

tx_ptp_pcslane_out

Port Changes

  • Added 32-bits to tx_axis_tdata_* and rx_axis_tdata_*
  • Updated bus sizes for many signals
  • Updated bus sizes of tx_axis_tdata_* and rx_axis_tdata_*.
  • Added 32/64-bit to tx_clk_out_* and tx_mii_out_*.
  • Added 32 bits to rx_serdes_data_out_* and tx_serdes_data_in_*.
  • Replaced "Ethernet MAC+PCS/PMA" with “Ethernet MAC+PCS/PMA-32/64-bit” in most of the signals in Core xci Top Level Port List.
  • Inserted "or Ethernet MAC" in most of the signals in Core xci Top Level Port List.
  • Updated descriptions of the following:
    • rx_axis_tdata[63 or 31:0]
    • rx_axis_tkeep[7 or 3:0]
    • ctl_rx_ignore_fcs
    • ctl_rx_max_packet_len[14:0]
    • ctl_rx_min_packet_len[7:0]
    • stat_rx_undersize
    • stat_rx_fragment
    • stat_tx_total_bytes[3:0]
    • stat_tx_frame_error
    • ctl_tx_pause_quanta[8:0][15:0]
    • ctl_tx_pause_refresh_timer[8:0][15:0]
    • ctl_an_nonce_seed[7:0]
    • rx_mii_clk
    • tx_mii_d_*
    • tx_mii_c_*
    • rx_mii_d_*
    • rx_mii_c_*

Registers Added

  • USER_REG_1: 0188
  • CORE_SPEED_REG:018C

Register Changes