| Bits | Default | Type | Signal |
|---|---|---|---|
| 0 | 0 | RW | rx_serdes_reset |
| 28 | 0 | RW | ctl_an_reset Note: This is a clear on write register.
This is available only when the Auto Negotiation/Link Training Logic feature is selected |
| 29 | 0 | RW | tx_serdes_reset |
| 30 | 0 | RW | rx_reset |
| 31 | 0 | RW | tx_reset |