Introduction - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English

The Xilinx® QDMA Subsystem for PCI Express ( PCIe® ) implements a high performance DMA for use with the PCI Express® 3.x Integrated Block with the concept of multiple queues that is different from the DMA/Bridge Subsystem for PCI Express which uses multiple Xilinx Card to Host (C2H) and Host to Card (H2C) channels.

This guide covers the QDMA Subsystem for PCIe for UltraScale+ devices. For details about the Versal® ACAP subsystem, refer to the Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344).