Gen3x16 capability requires a minimum of a -2 speed grade.
| Capability Link Speed | Capability Link Width | Supported Speed Grades |
|---|---|---|
| UltraScale+™ Devices with PCIE4 Block | ||
| Gen1/Gen2 | x1, x2, x4, x8, x16 | -1, -1L, -1LV, -2, -2L, -2LV, -3 |
| Gen3 | x1, x2, x4 | -1, -1L, -1LV, -2, -2L, -2LV, -3 |
| x8 | -1, -2, -2L, -3 | |
| x16 | -2, -2L, -3 | |
| UltraScale+ Devices with PCIE4C Block | ||
| Gen1/Gen2 | x1, x2, x4, x8, x16 | -1, -2, -2L, -2LV, -3 |
| Gen3 | x1, x2, x4 | -1, -2, -2L, -2LV, -3 |
| x8 | -1, -2, -2L, -3 | |
| x16 | -2, -2L, -3 | |
| Gen4 1 | x1, x2, x4, x8 | -2, -2L, -3 |
|
||
Note: This IP supports all
UltraScale+™
devices with PCIe blocks, except the
following:
- Zynq UltraScale+ MPSoC devices ZU5 and smaller
- Kintex UltraScale+ FPGA devices KU3 and smaller
- Artix UltraScale+ FPGA devices AU25P and smaller