Register Space - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English

This section provides register space information for the QDMA Subsystem for PCIe.

In register space descriptions, configuration register attributes are defined as follows:

NA
Reserved
RO
Read-Only - Register bits are read-only and cannot be altered by the software.
RW
Read-Write - Register bits are read-write and are permitted to be either Set or Cleared by the software to the desired state.
RW1C
Write-1-to-clear-status - Register bits indicate status when read. A Set bit indicates a status event which is Cleared by writing a 1b. Writing a 0b to RW1C bits has no effect.
W1C
Non-readable-write-1-to-clear-status - Register will return 0 when read. Writing 1b Clears the status for that bit index. Writing a 0b to W1C bits has no effect.
W1S
Non-readable-write-1-to-set - Register will return 0 when read. Writing 1b Sets the control set for that bit index. Writing a 0b to W1S bits has no effect.