Clock Jitter - 2022.1 English

Vivado Design Suite User Guide: Using Constraints (UG903)

Document ID
UG903
Release Date
2022-06-01
Version
2022.1 English

For ASIC devices, clock jitter is usually represented with the clock uncertainty characteristic. However, for Xilinx FPGAs, the jitter properties are predictable. They can be automatically computed by the timing analysis engine, or be specified separately.