Split-Termination DCI (Thevenin Equivalent Termination to V CCO /2)

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID

UG571

Release Date

2023-08-31

Revision

1.15 English

Some I/O standards (HSTL and SSTL) require an input termination resistance (R) to a V _TT voltage of V _CCO /2 (see This Figure ).

Figure 1-10: Input Termination to V _CCO / 2 without DCI (where R = Z ₀ )
X-Ref Target - Figure 1-10

Split-termination DCI creates a Thevenin equivalent circuit using two resistors of twice the resistance value (2R). One terminates to V _CCO , the other to GND. Split-termination DCI provides an equivalent termination to V _CCO /2 using this method. The 2R termination resistance is set by programming the ODT attribute. The resistors to V _CCO and GND are equal to twice the value set by ODT. For example, to achieve the Thevenin equivalent parallel-termination circuit of approximately 50 Ω to V _CCO /2, a 240 Ω external precision resistor is required at the VRP pin and ODT is set to RTT_48. Possible values for ODT for split-termination DCI are RTT_40, RTT_48, or RTT_60.

The DCI input standards supporting split termination are shown in Table: All DCI I/O Standards Supporting Split-Termination DCI .

Table 1-3: All DCI I/O Standards Supporting Split-Termination DCI
HSTL_I_DCI	DIFF_HSTL_I_DCI	SSTL18_I_DCI	DIFF_SSTL18_I_DCI
HSTL_I_DCI_18	DIFF_HSTL_I_DCI_18	SSTL15_DCI	DIFF_SSTL15_DCI
HSTL_I_DCI_12 (UltraScale devices only)	DIFF_HSTL_I_DCI_12 (UltraScale devices only)	SSTL135_DCI	DIFF_SSTL135_DCI
		SSTL12_DCI	DIFF_SSTL12_DCI

This Figure illustrates split-termination DCI.

Figure 1-11: Input Termination to V _CCO / 2 Using Split-Termination DCI (where R = Z ₀ )
X-Ref Target - Figure 1-11