Navigating Content by Design Process - 2021.1 English

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal™ ACAP design process Design Hubs can be found on the Xilinx.com website. This document covers the following design processes:

System and Solution Planning

Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:

• Design Flows
• RTL-to-Bitstream Design Flow
• Alternate RTL-to-Bitstream Design Flows

Hardware, IP, and Platform Development​

Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

• Accelerated Kernel Flows

System Integration and Validation​

Integrating and validating the system functional performance, including timing, resource use, and power closure. Topics in this document that apply to this design process include:

• Running Logic Simulation
• Logic Simulation

Board System Design

Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. Topics in this document that apply to this design process include:

• Xilinx Platform Board Support
• Board Files