The Configuration tab page provides core related configuration parameters. The subsystem configuration screen is shown in This Figure .
Pixel Format : Select Data Type (pixel format) as per the CSI-2 protocol (RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RGB888, RGB666, RGB565, RGB555, RGB444, YUV422_8bit). This selection is not considered by the subsystem when Include Video Format Bridge is disabled.
YUV420 word count: Select the maximum Y-line word count in bytes when YUV420 pixel format is selected.
Note: Ensure that the Y-line word count of the incoming data is at least 8 bytes less than the selected value to avoid the YUV420 WC Error interrupt.
Serial Data Lanes : Select the maximum number of D-PHY lanes for this subsystem instance. Values are 1, 2, 3, or 4.
Include Video Format Bridge (VFB) : Option to include or exclude the Video Format Bridge core in the subsystem. When this option is disabled, the Pixel Format selection is not considered by the subsystem. You can configure the stream data width (TDATA) when this option is disabled.
Support CSI Spec V2_0 : Select to enable CSI V2.0 features (RAW16, RAW20 support and VCX feature support).
Support VCX Feature : Option to include or exclude VCX feature.
Line Rate (Mb/s) : Enter a line rate value in megabits per second (Mb/s) within the valid range: 80 to 3200 Mb/s, based on the device selected. The Vivado IDE automatically limits the line rates based on the selected device. For details about family/device specific line rate support, refer to the data sheet for your device.
D-PHY Register Interface : Select to enable the register interface for the MIPI D-PHY core.
Enable Deskew Detection : Select to enable Deskew sequence detection and center alignment of clock and data lanes in the MIPI D-PHY core.
Note: Applicable only for UltraScale+ devices with line rates above 1500 Mb/s.
Note: The Xilinx ® MIPI D-PHY RX IP has specific periodic deskew length requirements. The minimum required length of the periodic pattern is 2 13 UI.
Calibration Mode: Select the calibration for 7 series MIPI D-PHY RX Subsystem. Values are None, Fixed, or Auto. When set to None, the Calibration Mode does not add IDELAY2 primitive. Fixed as Calibration Mode will set IDELAYE2 TAP value set in IDELAY Tap Value . Auto as Calibration Mode will add IDELAYE2 primitive and tap value will be configured by D-PHY RX IP based on received traffic and calibration algorithm.
External IDELAY tap loading: Allows to load IDELAY tap values through external ports in "Fixed" mode of Calibration.
Note: It is recommended to clock these ports through dphy_clk_200M.
IDELAY Tap Value: Select the IDELAY TAP value used for calibration in Fixed mode. Value in the range, 1 to 31.
Include IDELAYCTRL in core: Select to include IDELAYCTRL in core. Only available in FIXED and AUTO calibration modes. For multiple MIPI CSI-2 Rx IP cores that are sharing single IO bank, select Include IDELAYCTRL option in the IP for the auto calibration mode. Only one IDELAYCTRL is available per a single clock region. If multiple MIPI CSI-2 RX cores exist in single clock region, select this option for only one MIPI CSI-2 RX IP core. For the rest of MIPI CSI-2 RX cores, this option should be unselected.
Note: This option is applicable only for 7 series MIPI CSI-2 RX IP configurations.
Note: For 7 series in AUTO Mode, when there are multiple instances of DPHY and they share the IDELAY control Ready from one DPHY Instance to other DPHY Instance. The DPHY Instance which shares the IDELAY Controller Ready cannot have Parameter “Enable 300 MHz clock for IDELAYCTRL” set to true.
Note: For 7 series, the IP core is tested and validated at a maximum frequency of 1250 Mb/s; 1500 Mb/s is available in the GUI only for testing.
IODELAY_GROUP Name: This parameter is used to select the IODELAY_GROUP Name for the IDELAYCTRL. All core instances in the same bank sharing IDELAYCTRL should have the same name for this parameter. Select a unique name per bank.
Note: Available only for 7 series configurations.
Enable 300 MHz clock for IDELAYCTRL: Select to enable external 300 MHz clock port. Only available in AUTO calibration mode. This 300 MHz port is used for connecting to IDELAYCTRL . When you disable this option, IDELAYCTRL uses 200 MHz clock ( dphy_clk_200M ).
CSI2 Controller Register Interface: Unselect to remove the MIPI CSI-2 RX Controller register interface. Disabling this option improves resource count. When the CSI-2 RX Controller register interface is disabled, the core allows enabling/disabling the core through external ports. Also, some key status information is made available as external ports of the core. See Port Descriptions section for details of ports available when this option is unselected.
Embedded non-image Interface : Select to process and offload embedded non-image CSI-2 packets (with data type code 0x12) using a separate AXI4-Stream interface. If unselected, such packets are not processed and are ignored by the CSI-2 RX controller.
Filter User Defined data types : Select to Filter user defined data types (0x30 to 0x37) and do not output on Image interface (unsupported ErrId ISR will not be set even filtering is enabled). If unselected, such packets are processed and presented on image interface.
Line Buffer Depth : Depth of internal RAM used to accommodate throttling on the output video interface. Values are 128, 256, 512, 1024, 2048, 4096, 8192, or 16384. User can set this to the lowest value possible (e.g., 128), that will not cause line buffer full condition.
Note: There is no throttling allowed on the input to the PPI.
Pixels Per Clock : Select the number of pixels to output per clock on output interface. Values are 1 (single pixel), 2 (dual pixel), or 4 (quad pixel).
TUSER Width : Width of the sideband signal [TUSER] to report information like the line number, frame number, ECC, and CRC.
Allowed VC : Select the VC values to be used to while processing the packets. Values are All, 0, 1, 2, or 3.
Enable CRC : When set, CRC computation is performed on the packet payload and any errors are reported.
Enable Active Lanes : When set, the core supports the dynamic configuration of the number of active lanes from the maximum number of lanes selected during core generation using the parameter Serial Data Lanes . For example, when Serial Data Lanes is set to 3, the number of active lanes can be programmed using the protocol configuration register to be 1, 2, or 3. The core reports an error when the active lanes setting is greater than the serial lanes setting through the interrupt status register, bit-21.