Device, Package, and Speed Grade Selections - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

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5.1 English

The maximum possible line rate per lane is dependent on device selected.

For details about family/device specific line rate support refer UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 16] . See the respective Xilinx 7 series FPGA family device data sheet for details on the upper line rate limits.