Latency - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

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5.1 English

The CSI-2 RX Subsystem core latency is the time from the start-of-transmission (SoT) pattern on the serial lines to the tvalid signal assertion at CSI-2 RX Subsystem output. This includes the D-PHY latency, MIPI RX Controller latency and VFB latency (if the Video Format Bridge is included in the subsystem).

This Figure represents the latency calculation for the subsystem.

Figure 2-1: MIPI CSI-2 RX Subsystem Latency Calculation

X-Ref Target - Figure 2-1